Die-stacking technology is expanding the space diversity of on-chip communications by\nleveraging through-silicon-via (TSV) integration and wafer bonding. The 3D network-on-chip\n(NoC), a combination of die-stacking technology and systematic on-chip communication\ninfrastructure, suffers from increased thermal density and unbalanced heat dissipation across multistacked\nlayers, significantly affecting chip performance and reliability...................
Loading....